The invention relates to automatic gain control in signal receivers.
High-speed digital systems such as memory systems sometimes use a form of I/O in which data is defined by a differential voltage signal. A differential voltage signal comprises a pair of complementary signals. A high logic level is represented by setting a first of the signals to a relatively high voltage and the second of the signals to a relatively low voltage. A low logic level is represented by switching the two voltages, so that the first signal has a relatively lower voltage than the second signal. Differential signaling is advantageous because of its relative immunity to noise and other signal degradations. A disadvantage of differential signaling is that it requires two signal lines for every data bit.
In order to reduce the number of data signaling lines, single-ended signaling is often used in high speed circuits. This particular type of signaling is non-differential, although it is sometimes referred to as xe2x80x9cpseudo differentialxe2x80x9d signaling. Pseudo differential signaling specifies logic levels as voltages relative to a common, intermediate reference voltage. For example, a signal might be defined to represent a high logic level whenever its voltage is above the reference voltage, and to represent a low logic level whenever its voltage is below the reference voltage. This type of signaling requires fewer conductors than differential signaling, because a single reference line can be used in conjunction with many data signal lines. Although this type of signaling is less immune to signal degradation than differential signaling, it represents a distinct improvement over signaling systems in which signal levels are specified in terms of absolute voltages, rather than in relation to a specified reference voltage. Typically, a reference voltage signal is transmitted alongside data signals so that the same sources of noise will affect both the reference signal and the data signals. This tends to cancel the effects of the noise and provides some degree of noise immunity.
Regardless of whether signals are differential or non-differential, it is frequently desirable to perform some sort of signal buffering and/or conditioning at the receiving device. This is typically accomplished by a data receiver corresponding to each incoming signal line.
FIG. 1 shows a data receiver 10 that buffers an incoming data signal DIN to form a buffered or amplified internal data signal DOUT. This circuit uses automatic gain control to achieve a desired voltage amplitude at DOUT.
Data receiver 10 comprises a variable gain amplifier 12 that receives DIN and produces DOUT. The receiver also has an envelope detector 14 that detects the voltage amplitude of signal DOUT. An envelope detector or peak detector is a well-known type of circuit whose output voltage tracks the peak or swing voltages of a modulating input voltage such as a data signal.
FIG. 2 shows a simplified example of an envelope detector 14, comprising an FET control transistor M, a tracking capacitance C, a charging current source ICH, and a discharging current source IDIS. Transistor M is controlled by data signal DOUT to charge capacitance C whenever DOUT is relatively high. When the voltage VENV on capacitance C approaches the voltage of DOUT, the transistor shuts off because of the reduced gate-to-source voltage of the transistor in this condition. Thus, the transistor charges capacitance C to approximately the xe2x80x9chighxe2x80x9d logic level of DOUT. The size of current source ICH determines the xe2x80x9cattackxe2x80x9d rate of the envelope detectorxe2x80x94the rate at which output voltage VENV will climb in response to an increased voltage at DOUT. Current source IDIS is connected to slowly discharge capacitance C, to account for situations in which the peak levels of DIN decrease over time. The size of current source IDIS determines the xe2x80x9cdecayxe2x80x9d rate of the envelope detectorxe2x80x94the rate at which output voltage VENV will fall in response to a decreased input voltage DOUT. IDIS is chosen to be small enough so that the voltage at DOUT will remain close to its peak value between peaks that occur in DIN.
If appropriate sizes are selected for current sources ICH and IDIS, an envelope detector can be configured to produce an output that closely tracks the peak voltages of a data signal. Although the envelope detector of FIG. 2 is configured to detect positive signal peaks, the circuit can be easily altered to detect negative peaks in an input signal.
Referring again to FIG. 1, envelope detector 14 is configured to determine and track the peak voltage of output signal DOUT, and to produce a voltage signal VENV representing this peak voltage. A feedback component 20 receives VENV and compares it to a supplied reference amplitude VAMP. The output of feedback component 20 is connected to the gain control of amplifier 12, forming a feedback loop that operates to minimize any difference between the peak output VENV of signal DOUT and the supplied amplitude reference VAMP. In other words, this circuit sets the gain of amplifier 12 so that the peak voltage of output DOUT is approximately equal to the voltage of VAMP. In implementation, feedback component 20 is a gm stage whose output increases or decreases depending on the relative values of its inputs.
FIG. 3 shows data receiver 10, with the generic representation of amplifier 12 of FIG. 1 being replaced by a more detailed implementation of a differential amplifier circuit. Such a differential amplifier is typically used in conjunction with an input an input data signal DIN that is specified relative to an intermediate reference voltage VREF, which is relatively constant. The differential amplifier produces a differential voltage output DOUT having + and xe2x88x92 outputs.
The differential amplifier comprises a differential pair of FET transistors M2 and M3, whose sources are connected in common. The drains of M2 and M3 form the high and low outputs of differential voltage output signal DOUT, and are connected through respective loads R1LOAD and R2LOAD to a high supply voltage Vdd. The gates of M2 and M3 are connected respectively to DIN and VREF. The sources of M2 and M3 are connected in common through a biasing current source IBIAS to a low supply voltage Vss.
The input of envelope detector 14 is connected to the positive side of differential output DOUT. The output of feedback component 20 controls current source IBIAS, which in turn controls the gain of the amplifier circuit. Feedback component 20 receives the output of envelope detector 14 and the amplitude reference VAMP, and therefore establishes the gain of the amplifier circuit so that the peak voltage of output signal DOUT is approximately equal to VAMP.
The circuits described above have been used with success in many situations. However, problems arise in certain situations. One problem arises from the use of automatic gain control and envelope detectors in situations where there are relatively long periods without a transition in the received data signal. For example, a relatively long period in which a data signal remains low results in a decaying envelope voltage, which in turn causes automatic gain control circuits to inappropriately increase circuit gains. Furthermore, in many cases it is challenging to determine the optimal amplitude of DOUT. It is desirable to keep the amplitude as low as possible to reduce power consumption, but also to keep it as high as necessary to ensure accurate differentiation between high and low signals.
A further concern arises where a data signal is precisely timed relative to other signals. In cases such as this, it is important to maintain the relative timing between the two or more signals. However, variations in amplification can affect this timing. This problem arises, for example, with incoming signals that must exceed a certain threshold voltage in order for them to be resolved by receiving circuitry. In a situation like this, a signal having a relatively higher amplitude will be resolved more quickly than a signal having a relatively lower amplitude. Thus, differences, in amplification between two signals will be perceived as timing differences by receiving circuitry.
Differences in duty cycles between two signals can also affect their relative timings as perceived by receiving circuitry. This problem can arise in situations where one signal is a true differential voltage signal and the other is a non-differential or pseudo-differential voltage signal. A differential voltage signal typically achieves very close to a 50% duty cycle, even after amplification. Non-differential signals, however, are often subject to disproportionate amplification with respect to the positive and sides of their waveforms. This is especially true in circuits where reduced supply voltages are employed in order to increase circuit speeds. In such circuits, current sources sometimes begin to operate below saturation typically reducing the amount of amplification applied to negative portions of waveforms. This has the effect of changing the duty cycle of an amplified signal, which also changes the relative point in time at which the signal crosses specified voltage thresholds.
The circuits and techniques described below address these and other issues.